MOUNTAIN VIEW, Calif., Aug. 27, 2018 /PRNewswire/ -- Synopsys, Inc. (NASDAQ: SNPS), today announced a state-of-the-art artificial intelligence (AI) enabled formal verification app, Regression Mode Accelerator, as part of the Synopsys VC Formal® solution. This VC Formal app leverages state-of-the-art machine learning algorithms to deliver 10X speed-up in formal property verification during the design and verification cycle. Along with significant performance speed-up, use of this app accelerates formal property verification to achieve better convergence of formal proofs for subsequent runs. The Regression Mode Accelerator app also allows for significant saving of compute resources in nightly regressions for the verification of complex system-on-chip (SoC) designs to enable running formal verification in situations previously deemed impractical.
What is Formal Verification, Why is its Importance Increasing, and How is it Developing? John Franco Computer Science, University of Cincinnati. To prove that X does not have a property. A formal model obtained from a formal specification is. A formal functional verification application, JasperGold® Formal Property Verification App fully validates block-level properties and high-level requirements.
'As a leading integrated device manufacturer delivering solutions that are key to innovation and advancing the state-of-the-art in Smart Driving and the Internet of Things, including Smart Industry, ST's designers need a formal verification solution that provides best-in-class performance, ease-of-use, and quality of results,' said David Vincenzoni, R&D Design Manager at STMicroelectronics. 'The newly introduced VC Formal Regression Mode Accelerator app consistently delivered an order-of-magnitude performance improvement along with improved convergence of additional inconclusive properties for the most complex SystemVerilog Assertions on our design blocks.'
Increasing SoC complexity combined with rising time-to-market pressures are driving a continuous need for innovation in formal property verification performance and throughput. Synopsys VC Formal, with its comprehensive set of formal apps, including Property Verification (FPV), Sequential Equivalence Checks (SEQ), Register Verification (FRV), Formal Coverage Analyzer (FCA), Connectivity Checking (CC) and Automatic Extraction of Properties (AEP), has delivered faster property convergence for many different use cases at ST. The native integration of VC Formal with Synopsys' VCS® functional verification solution and Verdi® automated debug system enables design and verification teams to easily leverage formal technologies and automate root-cause analysis of formal results. Additionally, the native integration of VCS' robust coverage engines in VC Formal facilitates easy insertion of formal analysis into the existing verification environment.
'Machine-learning has emerged as a powerful technology for addressing the verification of highly-complex and leading-edge designs,' said Manish Pandey, Synopsys Fellow in the Verification Group. 'We have long collaborated with industry leaders like ST on the delivery of comprehensive verification solutions for advanced SoCs. Throughout these collaborations, we are broadening our investment in AI-enabled technologies into verification flows and methodologies, enabling faster time-to-market.'
Availability
The 2018.09 release of VC Formal with Regression Mode Accelerator is scheduled to be available in September 2018.
Additional Resources
For more information on VC Formal please visit:
InFormal Chat blog: https://blogs.synopsys.com/informal-chat/
VC Formal webpage: www.synopsys.com/vcformal
InFormal Chat blog: https://blogs.synopsys.com/informal-chat/
VC Formal webpage: www.synopsys.com/vcformal
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
Forward-Looking Statements
This press release contains forward-looking statements within the meaning of Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected release and benefits of the 2018.09 release of VC Formal with Regression Mode Accelerator. Any statements that are not statements of historical fact may be deemed to be forward-looking statements. These statements involve known and unknown risks, uncertainties and other factors that could cause actual results, time frames or achievements to differ materially from those expressed or implied in the forward-looking statements. Such risks and uncertainties include, among others, a customer's specific use cases, or the complexity of various SoC designs. Other risks and uncertainties that may apply are set forth in the 'Risk Factors' section of Synopsys' most recently filed Quarterly Report on Form 10-Q. Synopsys undertakes no obligation to update publicly any forward-looking statements, or to update the reasons actual results could differ materially from those anticipated in these forward-looking statements, even if new information becomes available in the future.
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SOURCE Synopsys, Inc.
Authors: Erik SeligmanTom SchubertM V Achutha Kiran Kumar
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Description
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.
- Learn formal verification algorithms to gain full coverage without exhaustive simulation
- Understand formal verification tools and how they differ from simulation tools
- Create instant test benches to gain insight into how models work and find initial bugs
- Learn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems
Readership
Professional engineers involved in chip design or verification
- Foreword for “Formal Verification: An Essential Toolkit for Modern VLSI Design”
- Acknowledgments
- Chapter 1. Formal verification: From dreams to reality
- What is FV?
- Why This Book?
- A Motivating Anecdote
- FV: The Next Level of Depth
- The Emergence of Practical FV
- Challenges in Implementing FV
- Amplifying the Power of Formal
- Getting the Most Out of This Book
- Practical Tips from This Chapter
- Further Reading
- Chapter 2. Basic formal verification algorithms
- Formal Verification (FV) in the Validation Process
- Comparing Specifications
- Formalizing Operation Definitions
- Boolean Algebra Notation
- BDDs
- Boolean Satisfiability
- Chapter Summary
- Further Reading
- Chapter 3. Introduction to systemverilog assertions
- Basic Assertion Concepts
- Immediate Assertions
- Sequences, Properties, and Concurrent Assertions
- Summary
- Further Reading
- Chapter 4. Formal property verification
- What is FPV?
- Example for this Chapter: Combination Lock
- Bringing Up a Basic FPV Environment
- How is FPV Different from Simulation?
- Summary
- Further Reading
- Chapter 5. Effective FPV for design exercise
- Example for This Chapter: Traffic Light Controller
- Creating a Design Exercise Plan
- Setting Up the Design Exercise FPV Environment
- Wiggling the Design
- Exploring More Interesting Behaviors
- Removing Simplifications and Exploring More Behaviors
- Summary
- Further Reading
- Chapter 6. Effective FPV for verification
- Deciding on Your FPV Goals
- Staging Your FPV Efforts
- Example for this Chapter: Simple ALU
- Understanding the Design
- Creating the FPV Verification Plan
- Removing Simplifications and Exploring More Behaviors
- Summary
- Further Reading
- Chapter 7. FPV “Apps” for specific SOC problems
- Reusable Protocol Verification
- Unreachable Coverage Elimination
- Connectivity Verification
- Control Register Verification
- Post-Silicon Debug
- Summary
- Further Reading
- Chapter 8. Formal equivalence verification
- Types of Equivalence to Check
- FEV Use Cases
- Running FEV
- Additional FEV Challenges
- Summary
- Further Reading
- Chapter 9. Formal verification’s greatest bloopers: The danger of false positives
- Misuse of the SVA Language
- Vacuity Issues
- Implicit or Unstated Assumptions
- Division of Labor
- Summary
- Further Reading
- Chapter 10. Dealing with complexity
- Design State and Associated Complexity
- Example for this Chapter: Memory Controller
- Observing Complexity Issues
- Simple Techniques for Convergence
- Helper Assumptions … and Not-So-Helpful Assumptions
- Generalizing Analysis Using Free Variables
- Abstraction Models for Complexity Reduction
- Summary
- Further Reading
- Chapter 11. Your new FV-aware lifestyle
- Uses of FV
- Getting Started
- Making Your Manager Happy
- What Do FVers Really Do?
- Summary
- Further Reading
- Index
Details
- No. of pages:
- 408
- Language:
- English
- Copyright:
- © Morgan Kaufmann 2015
- Published:
- 11th August 2015
- Imprint:
- Morgan Kaufmann
- eBook ISBN:
- 9780128008157
- Paperback ISBN:
- 9780128007273
Erik Seligman
Erik has worked at Intel Corporation in Hillsboro, Oregon for over two decades, in a variety of positions involving software, design, simulation, and formal verification. Currently he works in the Design Technology and Solutions division, where he supports formal verification usage for Intel teams worldwide. In his spare time he hosts the “Math Mutation” podcast, and serves as an elected director on the Hillsboro school board.
![Formal property verification Formal property verification](/uploads/1/2/5/0/125001598/791079888.jpg)
Intel’s Design Technology and Solutions division, supporting FV efforts for Intel projects worldwide
Tom Schubert
Tom recently joined the Electrical and Computer Engineering faculty at Portland State University and directs a graduate track in Design Verification and Validation. Previously, he was at Intel Corporation for 17 years in Hillsboro, Oregon, where he managed Intel's largest pre-silicon validation formal verification team develop and apply FPV techniques on multiple generations of microprocessor designs. Tom received a PhD in Computer Science from the University of California, Davis.
formerly at Intel, now directing the ECE graduate track in Design Verification and Validation at Portland State University, Portland, Oregon.
M V Achutha Kiran Kumar
Kiran has been working at intel India for past 11 years and has worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation and various levels of verification including formal verification. Currently he leads the formal verification efforts for the graphics design in Visual Platform Group and supports formal verification at intel india site.
Reviews
'...the authors thoroughly expressed their practical knowledge of this complex, and misunderstood topic, in an easy to read presentation...I strongly recommend this book to design and verification engineers who are contemplating, or are currently using formal verification...' --VerificationAcademy.com
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.'> Powered by
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JYOTI M.4 star rating
Easy to understand the concept of Formal Verification..
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